A photo mask is generally obtained by depositing a Cr (chromium) film on predetermined parts of a glass substrate, serving as light shielding parts. Parts of the glass substrate, not covered with the Cr film, serve as light transmitting parts. Exposure light is transmitted through these light transmitting parts or shielded with these light shielding parts, thus implementing transfer of predetermined mask patterns to a resist or the like as an object for exposure, formed on a semiconductor substrate (wafer). After the transfer of the mask patterns to the resist, patterning is executed on the photoresist, and a semiconductor device is fabricated using the resist as patterned.
The lithography tool's light source provides wavelength limited light to an illuminator. The illuminator is composed of mirrors and light pipes which shape the light to the necessary spatial uniformity and intensity across surface of the mask. Between the mask and the photoresist coated wafer is a lens. In the exposure step, the resist is irradiated with light from the illuminator through the photo mask, to the lens, then to the resist covered wafer surface. As a result, a latent image of the mask patterns is formed in the resist. Subsequently, upon the development of the resist, parts of the resist, corresponding to the latent image, selectively remain (positive resist) or are selectively removed (negative resist), thereby forming resist patterns on the wafer.
Advanced lithography is generally targeted at the limits of the best currently available lithography optics. The diffraction and contrast effects are limited by the numerical aperture (NA) of the lens, the wavelength of the light doing the exposure, and the properties of the resists for patterning a given level. Hole patterns (e.g. contacts and vias) are generally made by etching holes into layers of dielectrics (e.g. silicon oxide, silicon nitride, silicon oxynitride, etc.) using openings in the resists to determine where the holes will be opened. The best resists are generally positive resists. To make a hole using positive resist requires piling up light into a small spot to remove the resist. Piling up light is harder than its opposite, which is to provide complete darkness. Various physical effects, principally interference, can be used to help make darkness, but generally forcing photons into a small spot is difficult because of diffraction effects.
Along with microminiaturization of the mask pattern, the influence of the optical proximity effect becomes more pronounced, and consequently, the pattern fidelity deteriorates, thereby causing a problem that the resist pattern is found largely deviated from the mask pattern. Resist patterns obtained as a result of a simulation, would be identical in shape and size to respective image patterns without the influence of the optical proximity effect. However, in practice, the actual respective resist patterns obtained are found to be rounder (e.g. not vertical edges) or receding and in some cases merged or not fully opened as compared with the shape of the respective image patterns. Thus, pattern fidelity is found deteriorated due to these optical proximity effects.
Circuit designs generally place features such as contacts and vias at random locations, and conventional mask sets reflect this random nature. Such random placements (especially isolated or semi-isolated placements) have small depth of focus values, that is, they only fully remove the resist when the resist is almost exactly in the best focus plane of the exposure. Small depth of focus values are problematic for the desired wide manufacturing margins and can result in yield loss, such as due to highly resistive or electrically open contacts and vias.
Even certain regular feature patterns can be difficult to print, particularly when the pitch (center-to-center feature spacing) becomes small. For example, FIG. 1 shows a portion of a standard cell 100 having a pair of gate electrode (e.g. polysilicon) lines 103 and 104 aligned in the vertical direction each forming a complementary pair of transistors by extending from one active area (e.g. p-doped under the gates with n+ on both sides of the gates) 121 to another active area (e.g. n-doped under the gates with p+ on both sides of the gates) 131. As known in the art, sub-resolution assist features are provided on the mask (shown as circles) to provide diffraction support when printing tightly spaced circuit features. Such assist features generally are placed on the mask to provide the optimum diffraction effects to help print the desired regular feature patterns but are themselves chosen to be too small to expose the resist and thus to print on the circuit. Actual contacts for standard cell 100 are shown as squares having Xs inside.
The vertical distance (along the length of the gate lines) between S/D contacts 122 and 132 is shown as “2P”. In the vertical direction the minimum pitch between printed contacts, which is between the S/D contacts 122 and 132 and gate contacts 112, is ½ the distance between S/D contacts 122 and 132 and thus equal to “P”. However, in the horizontal direction, the minimum pitch, which is between S/D contacts 122 and 132 and gate contacts 112 is equal to P/2.
As known in the art, if circuit features such as the S/D contacts 122 and 132 and gate contacts 112 get too close in either the horizontal or the vertical direction relative to the capabilities of the lithography system, there will generally be insufficient contrast at each of the respective spots of light used for printing and the holes will become “blurred” together via the optical proximity effect. For example, in a current state of the art lithography system having a lens NA of 1.35 operating at λ=193 nm, the smallest feature pitch that can generally be printed is about ⅔λ, or about 130 nm.
As a result, for standard cell 100, S/D contacts 122 and 132 must generally be moved relatively far way in the vertical direction (e.g. from 2P to 4P) for printing problems associated with printing gate contacts at half pitch in the horizontal direction to be reduced. However, moving the S/D and gate contacts apart in the vertical direction undesirably lowers the density of the devices on the wafer, thus raising the cost per die.